Multi-protocol packet framing over an isochronous network

ABSTRACT

An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.

CROSS REFERENCE TO MICROFICHE APPENDIX

The microfiche appendix, which is a part of the present disclosure,entails one sheet of microfiche having a total of ninety-two (92)frames. The microfiche appendix contains RTL code and schematics of aspecific embodiment of an integrated circuit in accordance with thepresent invention. A portion of the disclosure of this patent documentcontains material which is subject to copyright protection. Thecopyright owner has no objection to the facsimile reproduction by anyoneof the patent document or the patent disclosure, as it appears in thePatent and Trademark Office patent files or records, but otherwisereserves all copyright rights whatsoever.

FIELD OF THE INVENTION

This invention relates to isochronous networks.

BACKGROUND INFORMATION

Ethernet is a well known network protocol. See the IEEE specification802.3 (the subject matter of which is incorporated herein by reference)for further background information on Ethernet. Ethernet is well suitedfor transferring large packets of information at spaced intervals.Information may, for example, be accumulated into a large packet andthen sent in a relatively large packet from one Ethernet node to anotherEthernet node. Ethernet can therefore be said to be a “bursty” networkprotocol.

Some types of information, such as the information in a typicaltelephone conversation, do not lend themselves to being accumulated overtime and then being transmitted as a single large packet. In a telephoneconversation, speech information should be passed from speaker tolistener without significant delay because the listener may use thatspeech information to formulate a response. Accordingly, there is nottime for large packets of information to be accumulated. Frequenttransmissions of small packets of information over the network isrequired. Ethernet is not well suited to this “nonbursty” type ofinformation transfer.

There are, however, communication protocols (called isochronousprotocols) which are suited for communication of such “nonbursty”information. Circuit switching and time division multiplexing (TDM)techniques are employed to divide a communication medium into a numberof consecutive frames, each frame including a number of time slots. Afirst telephone conversation may, for example, be allocated a first slotof each frame whereas a second telephone conversation may be allocated asecond slot of each frame. Because telephone information for eachconversation is received each frame, the “nonbursty” information of thetelephone conversations is communicated without significant delay.

Isochronous networks may also be made to carry “bursty” information.Telephone companies use an information framing protocol known as “HDLC”to frame information (“bursty” and/or “nonbursty”) for isochronouscommunication over a standard digital telephone line (an example ofwhich is Primary Rate ISDN or “PRI”). HDLC is part of a moreencompassing protocol called “X.25” See the document ISO/IEC 3309, 1991(the subject matter of which is incorporated herein by reference) foradditional information on the HDLC protocol.

FIG. 1 (Prior Art) shows an interconnection of networks. Telephoneinformation passes to and from telephones 1 and 2 over PBX (PrivateBranch Exchange) lines 3 and 4, respectively, to a local PBX 5. Thelocal PBX 5 is coupled to a central office/exchange 6 (typicallyoperated by a telephone company) via one or more PRI lines 7.“Nonbursty” telephone conversation information passes over thisstructure.

“Bursty” information such as video information and large computer files,on the other hand, passes over another structure. A first Ethernetnetwork 8 having a plurality of workstations and a file server and anEthernet hub is coupled to a second Ethernet network 9 via two Ethernetlines 10, 11 and an Ethernet hub/router 12. The file server of a networkmay, for example, store video data which can be accessed and displayedby the workstations of the network. Lines 10 and 11 are logically twodifferent Ethernet lines. Hub/router 12 is coupled to the centraloffice/exchange 6 via an isochronous link 13 such as a PRI line.Information is passed over link 13 using the HDLC protocol. The dots onselected workstations indicate video cameras.

A video camera of a workstation in the first Ethernet network cantherefore capture video information and store that information in thefile server of the first Ethernet network 8. A workstation in the secondEthernet network 9 can then access that information over Ethernet lines10 and 11 via hub/router 12 and display that information. A workstationcan also receive HDLC packaged “bursty” information (such as the yellowpages in graphic form) from the central office/exchange 6 viaisochronous link 13.

There exists, however, another information packaging protocol known asasynchronous transfer mode (hereinafter “ATM”). See the document “ATMUser-Network Interface Specification”, Version 3.0 (the subject matterof which is incorporated herein by reference) for additional informationon the ATM protocol. Although it is envisioned that ATM will eventuallyreplace HDLC, it is likely that significant numbers of ATM and HDLC datacommunication services will coexist for a significant period of time. Itwould therefore be desirable to provide network node hardware capable ofboth ATM and HDLC communication. Furthermore, a user using the structureof FIG. 1 would likely have a telephone on his/her desk in addition to aworkstation. Accordingly, a PBX line would extend onto the user's deskfor coupling to the telephone and an Ethernet line would also extendonto the user's disk for coupling to the workstation. It would bedesirable to eliminate one of these two lines so that the workstationcould receive both “bursty” Ethernet information and “nonbursty”telephone information over a single line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Prior Art) is a diagram showing an interconnection of Ethernetnetworks.

FIG. 2 is a diagram showing an isoENET network coupled to an Ethernetnetwork in accordance with an embodiment of the present invention.

FIG. 3 is a simplified block diagram of an expansion card for couplingan ISA parallel bus to an isochronous network in accordance with anembodiment of the present invention.

FIG. 4 is a simplified block diagram of an integrated circuit disposedon the expansion card of FIG. 3 in accordance with an embodiment of thepresent invention.

FIG. 5 is a more detailed block diagram illustrating a part of theintegrated circuit of FIG. 4 in accordance with an embodiment of thepresent invention.

SUMMARY

An integrated circuit has an isochronous network port for receivingisochronous information from an isochronous network. To allow theintegrated circuit to receive information packaged in accordance withtwo different packaging protocols (for example, HDLC and ATM), theintegrated circuit includes a first protocol packet framer/deframercircuit for deframing information packaged in accordance with a firstpackaging protocol (for example, HDLC) and a second protocol packetframer/deframer circuit for deframing information packaged in accordancewith a second packaging protocol (for example, ATM). A circuit switch isprovided to steer incoming information to the appropriate packetframer/deframer circuit depending on which slot of the network framecarried the information.

In some embodiments, the information received from the network is storedin an external memory after being deframed. A buffer manager circuit maybe provided on the integrated circuit to manage a circular inbound ringbuffer of information in the external memory. A device, such as a CPU,residing on a host bus coupled to the integrated circuit may then readthe information stored in the circular ring buffer via a parallel busport of the integrated circuit. An arbiter circuit on the integratedcircuit determines whether information from the framer/deframer circuitwill be written to the external memory or whether the device on the hostbus will read information from the external memory. In some embodiments,the integrated circuit includes a slot mapping memory which contains amap of which packet framer/deframer should be used for which slot. Theslot mapping memory can be programmed from the host bus of theintegrated circuit via the parallel bus port.

If information from the host bus is to be transmitted over the network,the information is written into the external buffer memory via theparallel bus port and the buffer memory port. The information is thenframed by the appropriate packet framer/deframer circuit and is suppliedto the isochronous network port of the integrated circuit via thecircuit switch. The buffer manager circuit of the integrated circuitdetermines how the information is written into an outbound buffer of theexternal memory from the host parallel bus port and how that informationis later read out of the outbound buffer and supplied to the packetframer/deframer circuit. The arbiter determines whether informationreceived from the parallel bus port will be written into the externalmemory or whether information from the external memory will be suppliedto the packet framer/deframer circuit for framing and transmission onthe isochronous bus.

Other associated structures and methods are also disclosed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An isochronous network specified by IEEE 802.9a (herein after referredto as “isoENET”) provides for transmission of both “nonbursty” and“bursty” information over a single Ethernet-compatible network. See thedocuments U.S. patent application Ser. No. 07/970,329 entitled“Frame-Based Transmission of Data”; IEEE specification 802.9a; and“IsoEnet Transforms LANs And WANs Into Interactive Multimedia Tools”,National Semiconductor Corporation, by Brian Edem et al., 1992 (thesubject matter of all three documents is incorporated herein byreference) for further information on the IsoENET isochronous network.

In an isoENET network, the information being transmitted is broken upinto a plurality of frames of information by a plurality ofsynchronization pulses. In addition to dedicated. Ethernet bandwidth,each frame contains 96 slots (also called “B-channels”). To transfer“bursty” information, multiple of these slots are filled with the burstyinformation. Several consecutive frames may be largely dedicated to thetransfer of a burst of information whereas subsequent frames (after theburst) may carry no “bursty” information. To transfer “nonbursty”information, on the other hand, one slot of each successive frame maycarry a small amount of “nonbursty” information. Accordingly,information from both a telephone and a workstation can be transferredover an isochronous network which is compatible with Ethernet.

FIG. 2 shows an example of an interconnection of networks and serviceswhich may be typical in the future. Network 100 is one Ethernet networkof the large installed base of Ethernet networks in use today. At leastsome of these installed Ethernet networks are likely to still beoperating in the future. Ethernet network 100 involves four workstations101-104 and an Ethernet hub 105. The workstations are coupled to the hubvia corresponding Ethernet lines which function as one logical wire.

Network 106 is an isoENET network which is capable of isochronousinformation transfer and is also compatible with the installed base ofEthernet networks. IsoENET network 106 includes four workstations107-110, a telephone 111, and an isoENET hub 112. Because isoENET iscapable of transmitting “nonbursty” telephone conversation information,telephone 111 is coupled to the isoENET network via workstation 107.

Video information (for example, MPEG encoded video) for display by theworkstations of the two networks is stored in this example in a videoserver 113. Programs for use by the workstations of the two networks arestored in this example in a file server 114. The servers 113 and 114 arecoupled to the two networks 100 and 106 via high speed 155 Mbps(megabits per second) fiber optic links 115-118 and an ATM switch 119.Accordingly, video information may be packaged in ATM format andtransmitted from the video server 113 in “bursty” fashion over 155 Mbpslink 118, 155 Mbps link 116, and isoENET line 107A to workstation 107.

A directory server 120 which supplies information in HDLC format may beprovided by a telephone company. Directory server 120 is coupled to acentral office/exchange 121 via a PRI line 122. The centraloffice/exchange 121 is coupled to the ATM switch via a 155 Mbps link123. Accordingly, information (such as yellow page graphic information)may be packaged in HDLC format and transmitted from the directory server120 in “bursty” fashion over PRI line 122, 155 Mbps link 123, 155 Mbpslink 116, and isoENET line 107A to workstation 107. Workstation 107therefore is an isoENET node capable of communicating using both ATM andHDLC protocols. The structure of workstation 107 is described in furtherdetail later.

Because network 100 is a standard Ethernet network which does notsupport “nonbursty” telephone conversation information, a telephone 124associated with workstation 101 is not coupled to a workstation ofnetwork 100 but rather is coupled to a PBX 125 via a PBX line 126.Because network 106 is an isoENET network, telephone 111 transmits andreceives “nonbursty” telephone conversation information via PBX-likeline 127, isoENET line 107A, and PRI line 128. PBX 125 is coupled to thecentral office/exchange 121 via multiple PRI lines 129.

FIG. 3 is a block diagram illustrating an expansion card 200 disposedinside workstation 107. See the document “HydraPro isoENET ISA CardProject Requirement Specification”, National Semiconductor Corporation,1994, (the subject matter of which is incorporated herein by reference)for additional information regarding a specific embodiment of expansioncard 200. Although FIG. 2 shows workstations as being the isoENET andEthernet nodes, it is to be understood that any suitable equipment mayserve as isoENET and Ethernet nodes. Personal computers, printers, andother peripherals may serve as nodes. The term “workstation” is used ina nonlimiting sense only as an illustrative example.

In FIG. 3, the expansion card 200 is coupled via a card edge connector(not shown) to the ISA parallel bus 201 on the motherboard of theworkstation 107. Video/audio I/O subsystems 203 are coupled to card 200via a MVIP (Multi-Vendor Integration Protocol) bus 204. Video/audio I/Osubsystems 203 may, for example, include a video camera, speakers, amicrophone, and a video compressor/decompressor for compressing dataoutput from the video camera for transmission on the MVIP bus 204 andfor decompressing compressed video data received from the MVIP bus 204.The MVIP bus is a known parallel isochronous bus used for movingisochronous data from one card to another card.

IsoENET line 107A of FIG. 2 actually is in this embodiment a twistedpair of physical wires 205. The block 206 of FIG. 3 labeled isoPhy is anintegrated circuit which performs the functions of level shifting andbuffering the isoENET network signals on physical wires 205 as well asseparating or combining Ethernet and B-channel data. See U.S. patentapplication Ser. No. 07/969,916 entitled “Network For Data CommunicationWith Isochronous Capability” (the subject matter of which isincorporated herein by reference) for additional information on isoPhyblock 206. An Ethernet subsystem integrated circuit 207 as well as anEthernet buffer 208 are disposed in the Ethernet data path betweenisoPhy block 206 and ISA bus 201. These parts perform the standardEthernet MAC (Media Access Control) function and manage transmit andreceive packet buffers. An integrated circuit 209 labeled isoBuffer, aB-channel buffer 210, and a multiplexer/demultiplexer 211 labeled isoMuxis disposed in the B-channel data path between isoPhy block 206 and ISAbus 201.

FIG. 4 is a logical block diagram illustrating the contents of theisoBuffer integrated circuit 209 of FIG. 3. See the document “isoBufferSpecification”, National Semiconductor Corporation, 1994 (the subjectmatter of which is incorporated herein by reference) for additionaldetails on a specific embodiment of integrated circuit 209. Integratedcircuit 209 includes a plug and play block 300, an isochronous databuffer manager block 301, and a circuit switch multiplexer/demultiplexerblock 302. At system boot, the central processing unit (not shown) ofthe workstation which is coupled to ISA bus 201 determines the needs andfunctions of card 200 via resource data stored in an EEPROM (not shown)on the card in accordance with the Microsoft Plug and PlaySpecification. Plug and play block 300 controls the EEPROM, decodes I/Oaddresses on the ISA bus, provides hardware chip selects for other chipson card 200, and routes interrupt requests to the appropriate IRQ linesof the ISA bus.

FIG. 5 is a block diagram illustrating blocks 301 and 302 of FIG. 4 ingreater detail. Information received from network wires 205 of FIG. 3 isreceived into the isoBuffer integrated circuit 209 on an isochronousnetwork port 400, proceeds through the isoBuffer as explained in furtherdetail below, and is written to external buffer memory 210 via a buffermemory port 401. The CPU of the workstation can later access thatinformation in external buffer memory 210 so that the information isread from buffer 210, passes through buffer memory port 401, and passesonto the ISA bus 201 via a parallel bus port 402. Information can alsoflow in the opposite direction such that information to be transmittedon network wires 205 is written by the CPU into the external buffermemory 210 via parallel bus port 402 and buffer memory port 401. Thisinformation is later read from the external buffer memory 210 and outputonto network wires 205 via buffer memory port 401 and isochronousnetwork port 400.

To allow workstation 107 (see FIG. 2) to receive and transmitinformation packaged in both HDLC and ATM protocols, isoBufferintegrated circuit 209 includes two HDLC packet framer/deframer circuits403 and 404, an ATM packet framer/deframer circuit 405, amultiplexer/demultiplexer 406, and a slot mapping memory 407. Packetframer/deframer circuits are known in the art. See the document “ATMOVERVIEW F-Fred Device-DP83372/R-Fred Device DP83382”, NationalSemiconductor Corporation, 1993 (the subject matter of which isincorporated herein by reference) for additional information pertainingto a packet framer/deframer circuit. A packet may, for example, consistof a handful to several thousand bytes of information. (Although a“framer/deframer” circuit does not really “frame” or “deframe”information but rather “packetizes” or “depacketizes” information, theterm “packetizer/depacketizer” is not is used herein because the term“packetizer” is not commonly used in the industry.)

Assume for illustrative purposes that isoENET frames are to be receivedfrom wires 205 of FIG. 3, that the first slot of each frame contains abyte of a packet framed in accordance with the HDLC protocol, and thatthe second slot in each frame contains a byte of a packet framed inaccordance with the ATM protocol. First, a 256 by 4-bit receive portionof the slot mapping memory 407 is initialized by the workstation CPUfrom the ISA bus 201 so that the contents of each of the 256 memorylocations of memory 407 indicates which of the packet framer/deframercircuits is to be used to deframe a corresponding one of the 256 slotsof a frame. The first memory location of memory 407 is programmed tocontain a value indicating that a HDLC packet framer/deframer circuit isto be used to frame or deframe information for the first slot whereasthe second memory location is programmed to contain a value indicatingthat the ATM packet framer/deframer circuit is to be used to frame ordeframe information for the second slot.

After this initialization of the slot mapping memory 407, a channelcounter (not shown) of circuit switch multiplexer/demultiplexer block302 provides addresses to the receive portion of the slot mapping memory407. Initially, the channel counter outputs a value which addresses thefirst memory location of the receive portion of memory 407. Because thefirst memory location of memory 407 was initialized to contain datawhich causes multiplexer/demultiplexer circuit 406 and HDLC packetframer/deframer circuit 404 to perform packet deframing, the first slotof the isoENET frame is deframed by HDLC packet framer/deframer circuit404. After the information from the first slot is received, the channelcounter is incremented. At the start of the second slot, the receiveportion of memory 407 is read using the incremented count value outputfrom the channel counter for the memory address. Because the secondmemory location of memory 407 was initialized to contain data whichcauses multiplexer/demultiplexer circuit 406 and ATM packetframer/deframer circuit 405 to perform packet deframing, the second slotof the isoENET frame is deframed by ATM packet framer/deframer circuit405. After the information from the second slot is received, the channelcounter is again incremented. Deframing of each successive slot of theisoENET frame proceeds in like fashion. The channel counter is reset bythe rising edge of the frame synchronization signal received on wires205 at the end of the frame. As an incoming packet is deframed, it isstored in a dedicated location in buffer 210.

When information is being written into buffer RAM 210 from one of thepacket framer/deframer circuits, a buffer manager in block 408 of theintegrated circuit determines where in memory 210 that information iswritten so that a separate receive ring buffer is maintained in memory210 for each packet framer/deframer. The location and size of each ringbuffer is set from the ISA bus by writing control registers in block408. Four control registers are associated with each packetframer/deframer circuit: a control register defining the beginninglocation of the ring buffer in physical memory 210, a control registerdefining the ending location of the ring buffer in physical memory 210,a control register defining where in memory 210 the next incoming packetis to be written, and a control register defining where in memory 210the oldest packet unread by the CPU is located. After an entire packethas been received and deframed by the appropriate packet framer/deframercircuit, the CPU is signalled via the ISA bus 201 that packet receptionis complete. The CPU can then commence in the transfer of the packetdata stored in buffer 210 to system memory via the ISA bus 201.

The block 408 actually includes two independent buffer managers. Eachbuffer manager is coupled to an associated packet framer/deframercircuit. Two HDLC packet framer/deframer circuits 403 and 404 areprovided in the specific embodiment in order to support a specific videoconferencing method. The present invention is not, however, limited torequire two packet framer/deframers for the same protocol.

In some embodiments, block 408 also includes circuitry for managing a“receive cell buffer” in memory 210. The receive cell buffer can be usedas a receptacle for ATM cells (a “cell” is an ATM construct and is 53bytes of ATM information). When an ATM cell is received that is not partof a packet of information being written into a receive ring buffer, theATM cell may be stored in the receive cell buffer. These stored ATMcells can then be accessed later via the ISA bus 201. Such ATM cellsmay, for example, be intermittently transmitted ATM cells which indicatethe status of a conference call when the conversation of the conferencecall itself is being written into a receive ring buffer in memory 210.The receive cell buffer makes use of hardware in an ATM packetframer/deframer circuit which identifies cells from raw incoming databut does not utilize the higher level deframing hardware whichidentifies, packets of cells.

IsoBuffer integrated circuit 209 also includes a constant bit rate (CBR)buffer manager block 410 which manages raw unframed or nondeframedstreams of data. The CBR buffer manager 410 keeps track of where astream of raw data is being written into memory 210 by tracking frames(frames usually are transmitted at a 8 kHz rate) rather than by trackingthe beginning and ending of packets. Given the number of bytes in aframe, and the starting location in memory 210, CBR buffer manager 410can determine from the number of frames received the location at whichraw nondeframed information is being written into memory 210.Nondeframed data in memory 210 may be deframed later in software by aCPU coupled to ISA bus 201. This constant bit rate buffer feature may beused to support a high level protocol which is not supported in hardwareon integrated circuit 209 by a dedicated packet framer/deframer circuit.

Arbiter 409 determines which of the ISA bus 201, the buffer managers inblock 408, or the CBR buffer manager 410 will have access to the bufferRAM 210. Any number of arbiter circuits can be used for this purpose. Inone embodiment, each of the blocks 408, 410 and an ISA bus interface 411provides a request signal on its own dedicated request line to thearbiter 409.

The microfiche appendix contains RTL code and schematics describing aspecific embodiment of an integrated circuit which is described in blockdiagram form by FIGS. 3-5. The RTL code specifies blocks 403-408 of FIG.5 whereas the schematics specify blocks 409-411. It is to be understoodthat the block diagram of FIG. 5 is illustrative of the functions of thevarious blocks and does not necessary indicate physical connectionsbetween the hardware circuits. In some embodiments,multiplexer/demultiplexer 406 is not disposed in the data path betweenthe isochronous network port of the integrated circuit and the packetframer/deframer circuits of the integrated circuit but rather the packetframer/deframer circuits are all coupled substantially directly to theisochronous network port and appropriate ones of the packetframer/deframer circuits are enabled one at a time bymultiplexer/demultiplexer 406. Similarly, the buffer managers in block408 and the CBR buffer manager in block 410 are not actually physicallydisposed in the illustrated data paths to buffer memory port 401 butrather are associated with information transfers through these paths. Insome embodiments, arbiter 409 includes a bidirectionalmultiplexer/demultiplexer for coupling a selected data path to buffermemory port 401. The selected data path may extend from ISA bus 201,from isochronous network port 400, or from one of the packetframer/deframer circuits 403-405. In some embodiments a multiplexer inblock 406 selectively couples the respective outputs of the framers inblocks 403-405 to an output part of port 400 whereas a demultiplexer inblock 406 simultaneously selectively couples an input part of port 400to the deframers in blocks 403-405.

Although the invention is described in connection with certainillustrative embodiments for instructional purposes, the invention isnot limited thereto. In some embodiments, the buffer memory is disposedon the same integrated circuit as the packet framer/deframer circuitsand the circuit switch multiplexer/demultiplexer. Buses other than theISA bus can be supported including the PCI bus and the Apple NuBUS.Accordingly, modifications, adaptations, and combinations of variousaspects of the specific embodiments can be practiced without departingfrom the scope of the invention as set forth in the following claims.

1. An integrated circuit, comprising: an isochronous network port; afirst protocol packet framer/deframer circuit; a second protocol packetframer/deframer circuit; and a circuit switch multiplexer/demultiplexercoupled to said isochronous network port, said first protocol packetframer/deframer circuit, and said second protocol packet framer/deframercircuit, wherein said circuit switch multiplexer/demultiplexer comprisesa multiplexer/demultiplexer, and a storage device, saidmultiplexer/demultiplexer being at least in part controlled based on avalue output from said storage device.
 2. The integrated circuit ofclaim 1, wherein a plurality of isochronous frames are received on saidisochronous network port, each of said isochronous frames comprising aplurality of slots, a first of said slots of a frame being supplied toand deframed by said first protocol packet framer/deframer circuit, asecond of said slots of said frame being supplied to and deframed bysaid second protocol packet framer/deframer circuit.
 3. The integratedcircuit of claim 1, wherein said first protocol packet framer/deframercircuit deframes ATM formatted slots, and wherein said second protocolpacket framer/deframer circuit deframes HDLC formatted slots.
 4. Theintegrated circuit of claim 3, wherein said first protocol packetframer/deframer circuit deframes ATM cells.
 5. The integrated circuit ofclaim 3, wherein said first protocol packet framer/deframer circuitdeframes both ATM cells and ATM packets.
 6. The integrated circuit ofclaim 1, wherein said storage device comprises a plurality of memorylocations, and wherein said circuit switch multiplexer/demultiplexerfurther comprises: a receive counter, said receive counter beingincremented after a receipt of a slot of information received on saidisochronous network port, a count value output from said receive counterpointing to a corresponding memory location of said plurality of memorylocations of said storage device.
 7. The integrated circuit of claim 1,further comprising: a parallel bus port, said storage device beingaccessible from said parallel bus port.
 8. The integrated circuit ofclaim 1, further comprising: a parallel bus port; parallel bus interfacecircuitry coupled to said parallel bus port; a memory; and an arbitercircuit coupled to said parallel bus interface circuitry and to saidmemory, said arbiter arbitrating access to said memory.
 9. Theintegrated circuit of claim 8, further comprising: a buffer managercircuit coupled to said first protocol packet framer/deframer circuit,said second protocol packet framer/deframer circuit and to said arbitercircuit, said buffer manager circuit comprising: first and secondreceive pointer registers for pointing to a receive buffer in saidmemory; and first and second transmit pointer registers for pointing toa transmit buffer in said memory.
 10. The integrated circuit of claim 8,further comprising: means, coupled to said circuit switchmultiplexer/demultiplexer, for managing buffering of substantiallynondeframed isochronous network data in said memory.
 11. A method,comprising: deframing information of a slot of a frame of networkinformation using a first protocol packet deframer circuit; deframinginformation of another slot of said frame of network information using asecond protocol packet deframer circuit, said first and second protocolpacket deframer circuits both being disposed on the same integratedcircuit; incrementing a counter of said integrated circuit so that acount value output from said counter corresponds with a slot number ofthe slot being received into said integrated circuit; and using saidcount value to address a slot mapping memory of said integrated circuit.12. The method of claim 11, wherein said integrated circuit has aparallel bus port, said method further comprising: programming said slotmapping memory of said integrated circuit via said parallel bus port.13. The method of claim 11, further comprising: storing informationdeframed by said first protocol packet deframer circuit in a first ringbuffer; and storing information deframed by said second protocol packetdeframer circuit in a second ring buffer.
 14. An integrated circuit,comprising: a first packet deframer circuit which deframes informationin accordance with a first network protocol; a second packet deframercircuit which deframes information in accordance with a second networkprotocol; and means for causing said first packet deframer circuit todeframe information in a first isochronous network slot of a frame inaccordance with said first network protocol and for causing said secondpacket deframer circuit to deframe information in a second isochronousnetwork slot of said frame in accordance with said second networkprotocol, wherein said means comprises means for storing slot mappinginformation.
 15. The integrated circuit of claim 14, wherein said firstnetwork protocol is an ATM protocol and wherein said second networkprotocol is an HDLC protocol.
 16. An integrated circuit comprising: afirst packet deframer circuit which deframes information in accordancewith a first network protocol; a second packet deframer circuit whichdeframes information in accordance with a second network protocol; meansfor causing said first packet deframer circuit to deframe information ina first isochronous network slot of a frame in accordance with saidfirst network protocol and for causing said second packet deframercircuit to deframe information in a second isochronous network slot ofsaid frame in accordance with said second network protocol; means formanaging a receive ring buffer; a parallel bus port; and parallel businterface circuitry coupled to said parallel bus port.
 17. Theintegrated circuit of claim 14, further comprising: a first packetframer circuit which frames information in accordance with a networkprotocol; and a second packet framer circuit which frames information inaccordance with a network protocol, wherein said means for causingcomprises: a multiplexer having a first input lead, a second input lead,and an output lead, said first input lead being coupled to an outputlead of said first packet framer circuit, said second input lead beingcoupled to an output lead of said second packet framer circuit, and anoutput lead being coupled to an output part of an isochronous networkport of said integrated circuit; and a demultiplexer having an inputlead, a first output lead, and a second output lead, said input leadbeing coupled to an input part of said isochronous network port, saidfirst output lead being coupled to an input lead of said first packetdeframer circuit, and said second output lead being coupled to an inputlead of said second packet deframer circuit.
 18. An integrated circuit,comprising: an isochronous network port, wherein the isochronous networkport receives frame of information, said frame having a plurality ofnon-isochronous and isochronous slots, and each of said isochronousslots having information of one of at least a first protocol or a secondprotocol; a first protocol packet framer/deframer circuit; a secondprotocol packet framer/deframer circuit; and a circuit switchmultiplexer/demultiplexer coupled to said isochronous network port, saidfirst protocol packet framer/deframer circuit, and said second protocolpacket framer/deframer circuit, wherein the circuit switchmultiplexer/demultiplexer couples said isochronous first protocol slotsto the first protocol packet framer/deframer circuit and couples saidisochronous second protocol slots to the second protocol packetframer/deframer circuit.
 19. The integrated circuit of claim 18 furthercomprising: a first demultiplexer coupled to said isochronous networkport, wherein the first demultiplexer separates the non-isochronousslots from the isochronous slots, and the circuit switchmultiplexer/demultiplexer is coupled to the first demultiplexer.
 20. Theintegrated circuit of claim 18, wherein said circuit switchmultiplexer/demultiplexer comprises: a multiplexer/demultiplexer; and astorage device, said multiplexer/demultiplexer being at least in partcontrolled based on a value output from said storage device.
 21. Theintegrated circuit of claim 18, wherein a plurality of isochronous slotsare received on said isochronous network port, a first of saidisochronous slots of a frame being provided to and deframed by saidfirst protocol packet framer/deframer circuit, and a second of saidisochronous slots of said frame being provided to and deframed by saidsecond protocol packet framer/deframer circuit.
 22. The integratedcircuit of claim 18, wherein said first protocol packet framer/deframercircuit deframes ATM formatted slots, and wherein said second protocolpacket framer/deframer circuit deframes HDLC formatted slots.
 23. Theintegrated circuit of claim 22, wherein said first protocol packetframer/deframer circuit deframes ATM cells.
 24. The integrated circuitof claim 22, wherein said first protocol packet framer/deframer circuitdeframes both ATM cells and ATM packets.
 25. The integrated circuit ofclaim 20, wherein said storage device comprises a plurality of memorylocations, and wherein said circuit switch multiplexer/demultiplexerfurther comprises: a receive counter, said receive counter beingincremented after a receipt of a slot of information received on saidisochronous network port, a count value output from said receive counterpointing to a corresponding memory location of said plurality of memorylocations of said storage device.
 26. The integrated circuit of claim20, further comprising: a parallel bus port, said storage device beingaccessible from said parallel bus port.
 27. The integrated circuit ofclaim 20, further comprising: a parallel bus port; parallel businterface circuitry coupled to said parallel bus port; a memory; and anarbiter circuit coupled to said parallel bus interface circuitry and tosaid memory, said arbiter arbitrating access to said memory.
 28. Theintegrated circuit of claim 27, further comprising: a buffer managercircuit coupled to said first protocol packet framer/deframer circuit,said second protocol packet framer/deframer circuit and to said arbitercircuit, said buffer manager circuit comprising: first and secondreceive pointer registers for pointing to a receive buffer in saidmemory; and first and second transmit pointer registers for pointing toa transmit buffer in said memory.
 29. The integrated circuit of claim27, further comprising: means, coupled to said circuit switchmultiplexer/demultiplexer, for managing buffering of substantiallynondeframed isochronous network data in said memory.
 30. A method,comprising: framing network information, wherein network informationframes include non-isochronous and isochronous slots; deframinginformation of an isochronous slot of using a first protocol packetdeframer circuit; and deframing information of another isochronous slotusing a second protocol packet deframer circuit, said first and secondprotocol packet deframer circuits both being disposed on the sameintegrated circuit.
 31. The integrated circuit of claim 30, wherein saidfirst protocol packet framer/deframer circuit deframes ATM formattedslots, and wherein said second protocol packet framer/deframer circuitdeframes HDLC formatted slots.
 32. The method of claim 30 wherein eachisochronous slot is formatted with at least one of a first protocol or asecond protocol, the method further comprising the steps of: separatingthe non-isochronous slots from the isochronous slots into anon-isochronous data stream and an isochronous data stream; coupling theisochronous slots formatted with the first protocol to the firstprotocol packet deframer circuit; and coupling the isochronous slotsformatted with the second protocol to the second protocol packetdeframer circuit.
 33. The method of claim 32 further comprising the stepof: demultiplexing the isochronous slots; and wherein the separatingstep includes the step of demultiplexing with a first demultiplexer eachnetwork information frame.
 34. The method of claim 30 further comprisingthe steps of: flaming information having a first protocol using a firstprotocol packet framer circuit; framing information having a secondprotocol using a second protocol packet framer circuit; combining thefirst protocol framed information and the second protocol framedinformation into isochronous slots; and combining isochronous slots withnon-isochronous slots into a frame.
 35. The method of claim 30, furthercomprising: incrementing a counter of said integrated circuit so that acount value output from said counter corresponds with a slot number ofthe slot being received into said integrated circuit; and using saidcount value to address a slot mapping memory of said integrated circuit.36. The method of claim 35, wherein said integrated circuit has aparallel bus port, said method further comprising: programming said slotmapping memory of said integrated circuit via said parallel bus port.37. The method of claim 35, further comprising: storing informationdeframed by said first protocol packet deframer circuit in a first ringbuffer; and storing information deframed by said second protocol packetdeframer circuit in a second ring buffer.
 38. An integrated circuit,comprising: means for framing information, each information frame havingisochronous and non-isochronous slots and each of said isochronous slotshaving information formatted by one of at least a first network protocolor a second network protocol; means for receiving the framedinformation; means for separating the isochronous slots and thenon-isochronous slots; a first means for combining information formattedby a first protocol into a first packet; a second means for combininginformation formatted by a second protocol into a second packet; andmeans for coupling first protocol formatted information in anisochronous slot to the first means for combining and for couplingsecond protocol formatted information in another isochronous slot to thesecond means for combining.
 39. The integrated circuit of claim 38further comprising: a first means for separating a packet of informationformatted by a first protocol into first segments of information; asecond means for disassembling a packet of information formatted by asecond protocol into second segments of information; and means forcombining the first information segments and the second informationsegments into an isochronous data stream; means for combining theisochronous data stream with a non-isochronous data stream.
 40. Theintegrated circuit as in claim 39 wherein the means for combiningincludes the step of inserting the first segments and the secondsegments into isochronous slots of a frame and non-isochronous datastream segments into non-isochronous slots of the frame.
 41. Theintegrated circuit of claim 38, wherein said first network protocol isan ATM protocol and wherein said second network protocol is an HDLCprotocol.
 42. The integrated circuit of claim 38, wherein said means forcoupling comprises means for storing slot mapping information.
 43. Theintegrated circuit of claim 38, further comprising: means for managing areceive ring buffer; a parallel bus port; and parallel bus interfacecircuitry coupled to said parallel bus port.
 44. The integrated circuitof claim 38, further comprising: a first packet framer circuit whichframes information in accordance with a network protocol; and a secondpacket framer circuit which frames information in accordance with anetwork protocol, wherein said means for coupling comprises: amultiplexer having a first input lead, a second input lead, and anoutput lead, said first input lead being coupled to an output lead ofsaid first packet framer circuit, said second input lead being coupledto an output lead of said second packet framer circuit, and an outputlead being coupled to an output part of an isochronous network port ofsaid integrated circuit; and a demultiplexer having an input lead, afirst output lead, and a second output lead, said input lead beingcoupled to an input part of said isochronous network port, said firstoutput lead being coupled to an input lead of said first packet deframercircuit, and said second output lead being coupled to an input lead ofsaid second packet deframer circuit.
 45. An apparatus, comprising: anisochronous port; one or more first protocol packet framer/deframercircuits; one or more second protocol packet framer/deframer circuits;and a circuit switch multiplexer/demultiplexer coupled to theisochronous port, at least one of the first protocol packetframer/deframer circuits, and at least one of the second protocol packetframer/deframer circuits, wherein the circuit switchmultiplexer/demultiplexer comprises a multiplexer/demultiplexer and astorage device, the multiplexer/demultiplexer being at least in partcontrolled based on an output from the storage device.
 46. The apparatusof claim 45, wherein the isochronous port comprises a time divisionmultiplexed port.
 47. An apparatus, comprising: an isochronous port; afirst protocol circuit; a second protocol circuit; and a circuit switchmultiplexer/demultiplexer coupled to the isochronous port, the firstprotocol circuit, and the second protocol circuit, wherein the circuitswitch multiplexer/demultiplexer comprises a multiplexer/demultiplexerand a storage device, the multiplexer/demultiplexer being at least inpart controlled based on an output from the storage device.
 48. Theapparatus of claim 47, wherein the first protocol circuit manages rawdata.
 49. The apparatus of claim 47, wherein the first protocol circuitmanages unframed data.
 50. The apparatus of claim 47, wherein the firstprotocol circuit manages nondeframed data.
 51. The apparatus of claim47, wherein the first protocol circuit comprises a constant bit ratebuffer circuit.
 52. The apparatus of claim 47, wherein the secondprotocol circuit comprises a packet framer/deframer circuit.
 53. Theapparatus of claim 47, wherein the second protocol circuit comprises anHDLC framer/deframer circuit.
 54. The apparatus of claim 47, wherein thesecond protocol circuit comprises multiple packet framer/deframercircuits.
 55. The apparatus of claim 47, wherein the second protocolcircuit comprises multiple HDLC framer/deframer circuits.
 56. Theapparatus of claim 47, wherein the second protocol circuit comprises anasynchronous transfer mode framer/deframer circuit.
 57. The apparatus ofclaim 47, wherein the isochronous port comprises a time divisionmultiplexed port.
 58. An apparatus, comprising: an isochronous port; oneor more first protocol circuits; one or more second protocol circuits; acircuit switch multiplexer/demultiplexer coupled to the isochronousport, at least one of the first protocol circuits, and at least one ofthe second protocol circuits, wherein the circuit switchmultiplexer/demultiplexer comprises a multiplexer/demultiplexer and astorage device, the multiplexer/demultiplexer being at least in partcontrolled based on an output from the storage device; and a buffermemory, wherein a signal path is provided from the isochronous port toat least one of the first protocol circuits, and from the at least onefirst protocol circuit to the buffer memory, and from the buffer memoryto at least one of the second protocol circuits, and from the secondprotocol circuit to the isochronous port.
 59. The apparatus of claim 58,wherein at least one of the first protocol circuit manages raw data. 60.The apparatus of claim 58, wherein at least one of the first protocolcircuit manages unframed data.
 61. The apparatus of claim 58, whereinthe first protocol circuit manages nondeframed data.
 62. The apparatusof claim 58, wherein the first protocol circuit comprises a constant bitrate buffer circuit.
 63. The apparatus of claim 58, wherein the secondprotocol circuit comprises a packet framer/deframer circuit.
 64. Theapparatus of claim 58, wherein the second protocol circuit comprises anHDLC framer/deframer circuit.
 65. The apparatus of claim 58, wherein thesecond protocol circuit comprises multiple packet framer/deframercircuits.
 66. The apparatus of claim 58, wherein the second protocolcircuit comprises multiple HDLC framer/deframer circuits.
 67. Theapparatus of claim 58, wherein the second protocol circuit comprises anasynchronous transfer mode framer/deframer circuit.
 68. The apparatus ofclaim 58, wherein the isochronous port comprises a time divisionmultiplexed port.
 69. A method, comprising: deframing information of areceived slot of information using a first protocol packet deframercircuit; deframing information of another received slot of informationusing a second protocol packet deframer circuit; generating an outputthat corresponds with the slot being received; and using the output toaddress a slot mapping memory.
 70. An apparatus, comprising: a firstpacket deframer circuit which deframes information in accordance with afirst protocol; a second packet deframer circuit which deframesinformation in accordance with a second protocol; and means for causingthe first packet deframer circuit to deframe information in a firstisochronous slot of a frame in accordance with the first protocol andfor causing the second packet deframer circuit to deframe information ina second isochronous slot of the frame in accordance with the secondprotocol, wherein the means comprises means for storing slot mappinginformation.
 71. An apparatus comprising: a first packet deframercircuit which deframes information in accordance with a first protocol;a second packet deframer circuit which deframes information inaccordance with a second protocol; means for causing the first packetdeframer circuit to deframe information in a first isochronous slot of aframe in accordance with the first protocol and for causing the secondpacket deframer circuit to deframe information in a second isochronousslot of the frame in accordance with the second protocol; means formanaging a receive buffer; a port; and interface circuitry coupled tothe port.
 72. An apparatus comprising: a first packet deframer circuitwhich deframes information in accordance with a first protocol; a secondpacket deframer circuit which deframes information in accordance with asecond protocol; means for causing the first packet deframer circuit todeframe information in a first isochronous slot of a frame in accordancewith the first network protocol and for causing the second packetdeframer circuit to deframe information in a second isochronous slot ofthe frame in accordance with the second protocol; means for managing areceive buffer; a bus port for coupling to a bus; and interfacecircuitry coupled to the bus port, wherein the bus supports multipletransfer types, such as direct memory access, shared memory access orstandard I/O access.
 73. An apparatus, comprising: an isochronous port,wherein the isochronous port receives a frame of information, the framehaving a plurality of non-isochronous and isochronous slots, and each ofthe isochronous slots having information of one of at least a firstprotocol or a second protocol; a first protocol packet framer/deframercircuit; a second protocol packet framer/deframer circuit; and a circuitswitch multiplexer/demultiplexer coupled to the isochronous port, thefirst protocol packet framer/deframer circuit, and the second protocolpacket framer/deframer circuit, wherein the circuit switchmultiplexer/demultiplexer couples the isochronous first protocol slotsto the first protocol packet framer/deframer circuit and couples theisochronous second protocol slots to the second protocol packetframer/deframer circuit.
 74. A method, comprising: framing information,wherein information frames include non-isochronous and isochronousslots; deframing information of an isochronous slot of using a firstprotocol packet deframer circuit; and deframing information of anotherisochronous slot using a second protocol packet deframer circuit, saidfirst and second protocol packet deframer circuits being coupled to acommon buffer memory.
 75. An apparatus, comprising: means for framinginformation, each information frame having isochronous andnon-isochronous slots and each of the isochronous slots havinginformation formatted by one of at least a first protocol or a secondprotocol; means for receiving the framed information; means forseparating the isochronous slots and the non-isochronous slots; a firstmeans for combining information formatted by a first protocol into afirst packet; a second means for combining information formatted by asecond protocol into a second packet; and means for coupling firstprotocol formatted information in an isochronous slot to the first meansfor combining and for coupling second protocol formatted information inanother isochronous slot to the second means for combining.
 76. Anapparatus comprising: a network port; a multiplexer/demultiplexercircuit coupled to the network port; a first protocol circuit and asecond protocol circuit each coupled to the multiplexer/demultiplexercircuit; and a buffer coupled to the first and second protocol circuit;wherein a signal path is provided from the network port to the firstprotocol circuit, and from the first protocol circuit to the buffer, andfrom the buffer to the second protocol circuit, and from the secondprotocol circuit to the network port.
 77. The apparatus of claim 76,wherein the first protocol circuit manages raw data.
 78. The apparatusof claim 76, wherein the first protocol circuit manages unframed data.79. The apparatus of claim 76, wherein the first protocol circuitmanages nondeframed data.
 80. The apparatus of claim 76, wherein thefirst protocol circuit comprises a constant bit rate buffer circuit. 81.The apparatus of claim 76, wherein the second protocol circuit comprisesa packet framer/deframer circuit.
 82. The apparatus of claim 76, whereinthe second protocol circuit comprises an HDLC framer/deframer circuit.83. The apparatus of claim 76, wherein the second protocol circuitcomprises multiple packet framer/deframer circuits.
 84. The apparatus ofclaim 76, wherein the second protocol circuit comprises multiple HDLCframer/deframer circuits.
 85. The apparatus of claim 76, wherein thesecond protocol circuit comprises an asynchronous transfer modeframer/deframer circuit.
 86. The apparatus of claim 76, wherein thenetwork port comprises a time division multiplexed port.
 87. A methodcomprising: coupling information from a network to an isochronous port,the information including non-isochronous and isochronous slots;coupling the information from the isochronous port to amultiplexer/demultiplexer; selectively coupling the information from themultiplexer/demultiplexer to a first protocol circuit and a secondprotocol circuit; and selectively coupling the information from/to thefirst and second protocol circuit to a buffer; wherein a signal path isprovided from the isochronous port to the first protocol circuit, andfrom the first protocol circuit to the buffer, and from the buffer tothe second protocol circuit, and from the second protocol circuit to theisochronous port.
 88. The method of claim 87, wherein the first protocolcircuit manages raw data.
 89. The method of claim 87, wherein the firstprotocol circuit manages unframed data.
 90. The method of claim 87,wherein the first protocol circuit manages nondeframed data.
 91. Themethod of claim 87, wherein the first protocol circuit comprises aconstant bit rate buffer circuit.
 92. The method of claim 87, whereinthe second protocol circuit comprises a packet framer/deframer circuit.93. The method of claim 87, wherein the second protocol circuitcomprises an HDLC framer/deframer circuit.
 94. The method of claim 87,wherein the second protocol circuit comprises multiple packetframer/deframer circuits.
 95. The method of claim 87, wherein the secondprotocol circuit comprises multiple HDLC framer/deframer circuits. 96.The method of claim 87, wherein the second protocol circuit comprises anasynchronous transfer mode framer/deframer circuit.
 97. The method ofclaim 87, wherein the network port comprises a time division multiplexedport.